1. Field of the Invention
The present invention relates to an electrically rewritable non-volatile semiconductor storage device and a method of manufacturing the same.
2. Description of the Related Art
Conventionally, LSIs are formed by integration of devices in a two-dimensional plane on the silicon substrate. Although the dimension for each device must be reduced (refinement) to increase memory storage capacity, recent years are facing challenges in such refinement from the viewpoint of cost and technology. Such refinement requires further improvements in photolithography technology. However, in currently available ArF immersion lithography technology, for example, the resolution limit has been reached around the 40 nm design rule and so EUV exposure devices have to be introduced for further refinement. However, the EUV exposure devices are expensive and infeasible in view of the costs. In addition, if such refinement is accomplished, it is assumed that physical improvement limit, such as in breakdown voltage between devices, would be reached unless driving voltage can be scaled. Thus, it is likely that difficulties would be encountered in device operation itself.
Therefore, a large number of semiconductor storage devices have been proposed recently where memory cells are arranged in a three-dimensional manner to achieve improved integration of memory devices (see, Patent Document 1: Japanese Patent Laid-Open No. 2007-266143; Patent Document 2: U.S. Pat. No. 5,599,724; and Patent Document 3: U.S. Pat. No. 5,707,885).
One of the conventional semiconductor storage devices where memory cells are arranged in a three-dimensional manner uses transistors with a cylinder-type structure (see, Patent Documents 1-3). Those semiconductor storage devices using transistors with a SGT cylinder-type structure are provided with multiple conductive layers corresponding to gate electrodes and pillar-like columnar semiconductors. Each of the columnar semiconductors serves as a channel (body) part of each of the transistors. Charge accumulation layers are provided around the columnar semiconductors for accumulating charges. Such a configuration including conductive layers, columnar semiconductors, and charge trap layers are referred to as a “memory string”.
In the manufacturing process of the memory strings, after laminating multiple conductive layers and insulation layers, those steps are performed to flatten the surface by Chemical Mechanical Polishing (CMP). Such process, however, requires a large number of manufacturing steps and thus the cost of manufacturing the semiconductor storage devices would not be inexpensive.